Digital communication interfaces have become widespread with modern technology's emphasis on rapid transfer and communication of digital data for an ever-increasing amount of important functions including data storage, output transmission, and device control. These interfaces include standard communication specifications such as Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), Firewire®, etc. These interfaces are used in a number of applications for computers and other electronic devices.
USB, for example, is a commonly-used interface standard that allows data communication between a host and one or more peripheral devices. Communication in a USB interface can use a variety of formats and speeds. In general, “low speed” or “LS” has a data transfer rate of 1.5 Mbit/s, “full speed” or “FS” has a data transfer rate of 12 Mbit/s, “high speed” or “HS” has a data transfer rate of 480 Mbit/s, and “super speed” or “SS” has a data transfer rate of 5 Gbit/s.
A host controller can communicate with the peripheral devices using a USB communication interface. A USB communication interface (or “system”) can include one or more USB hubs that can connect multiple peripheral devices, in series, to the host. Typically, each USB hub has multiple downstream ports other USB hubs or directly to peripheral devices.
FIG. 1 (Prior Art) is a block diagram of a conventional USB hub 100 which includes an “upstream” Universal Serial Bus (USB) High Speed (HS) Analog Front End (AFE) (“USB HS AFE”) block 104, a “downstream” USB HS AFE block 106, and hub core 102. Although only a single downstream HS AFE block is shown, typically more than one can be present. HS AFE blocks 104 and 106 provide the analog interface for cables (not shown) connected to hub 100 from other outboard devices, a host device, or hubs, as well as the digital interface to the circuitry in the hub core 102. Although labeled as HS, blocks 104 and 106 can handle traffic at the slower speeds of LS and FS as well. Typically, the digital data busses connecting HS AFE blocks 104 and 106 to hub core 102 are based on the UTMI (USB Transceiver Macrocell Interface) protocol which may have as many as 40 or 50 interconnect lines.
The hub core 102 includes hub controller 108, which is used for various control functions of the hub, including receiving configuration commands from a host device (not shown) and maintaining communication with the host device. The transaction translator (TT) 110 is included in the hub core to respond to high speed (HS) split transactions and translate them (if needed) into full speed (FS) or low speed (LS) transactions compatible with any full-speed or low-speed devices attached on downstream-facing ports of the hub. Port routing logic 112 is included in the hub core to route high-speed packets between particular downstream ports and the upstream port, as well as distribute low-speed and full-speed packets between downstream ports and the transaction translator 110. Upstream port logic block 116 and downstream ports logic block 118 control the USB-specific signaling detected by and generated by the hub. Each hub 100 re-clocks data to provide its own locally-clocked output data (e.g., to control jitter) in upstream and downstream directions to provide a signal having the proper timing. The upstream and downstream ports logic blocks 116, 118 each include a clock and data recovery (CDR) block to recover the clock signal based on edges of the data stream, as well as an elasticity buffer to buffer the signal as needed for clock recovery.
Applications for USB communication interfaces (including USB hubs) are continually expanding with a wide variety of devices being equipped with USB interfaces. As these devices extend further from the host device, particularly in industrial environments, issues such as voltage spikes, ground loops, and surges can negatively impact the integrity of the data being transmitted over the USB bus. To address these issues, it would be desirable to have galvanic isolation incorporated with the USB communication interface.
Galvanic isolation typically prevents the interconnection of DC voltages and currents across the isolation interface. Low frequency AC voltages can also be isolated (such as 50-60 Hz line power frequencies) if the data being transmitted is of a considerably higher frequency. Devices such as coupling capacitors, transformers, or photo-optical devices are commonly used for galvanic isolation for high speed electronic data. Less common are the use of mechanical or sonic isolators, since their frequency response may be inadequate for high speed data transmission. Typically, industrial applications can require as high as 2500 Volts RMS isolation.
It has been found that galvanic isolation can introduce its own set of problems, particularly with high speed (480 MHz) USB devices. Placing any component, such as a transformer, in series with the data communication busses will introduce a transmission lag that will impact the relative timing (or jitter) of the signals.
The high speed USB specification has tightened up the jitter requirements significantly over the earlier “full speed” and “low speed” jitter requirements. As such, prior art devices that functioned properly at “full speed” and “low speed” due to relaxed jitter requirements can no longer function at the “high speed” data rates of 480 MHz. For example, Analog Devices part number AduM4160, which can operate at low speed or high speed, utilizes monolithic air core transformers which function as the isolation devices. When operating at high speed, and under certain conditions (e.g. with long cabling), this device may have difficulties in meeting USB transmission lag and jitter specifications.
These and other limitations of the prior art will become apparent to those of skill in the art upon a reading of the following descriptions and a study of the several figures of the drawing.